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Document Reference No.: FT_000166
V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 155
`
Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Description
CLKOUT period
CLKOUT high period
CLKOUT low period
CLKOUT to RXF#
CLKOUT to read DATA valid
OE# to read DATA valid
CLKOUT to OE#
RD# setup time
RD# hold time
CLKOUT TO TXE#
Write DATA setup time
Write DATA hold time
WR# setup time
WR# hold time
Min
-
9.38
9.38
1
1
1
1
12
0
1
12
0
12
0
Typical
20.83
10.42
10.42
-
-
-
-
-
-
-
-
-
-
-
Max
-
11.46
11.46
7.83
7.83
7.83
7.83
-
-
-
-
-
-
-
Uni
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 3.9 - Synchronous FIFO Mode Read and Write Cycle Timing
In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An
external device synchronises to the CLKOUT output and it also has access to the output enable OE# input
to control data flow. An external device should drive output enable OE# low before pulling RD# line
down.
When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when
there is still data to be read. Similarly when bursts of data are to be written to the module WR# should
be kept low. TXE# remains low when there is still space available for the data to be written
Copyright ? 2010 Future Technology Devices International Limited
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